Semiconductor chips typically comprise the bulk of the components in an electronic system. These semiconductor chips are also often the hottest part of the electronic system, and failure of the system can often be traced back to thermal overload on the chips. Thermal management of semiconductor chips is therefore a critical parameter of electronic design, as it influences the design of the cooling system for a computing device or system incorporating the semiconductor chip.
FIG. 1 is a schematic diagram illustrating an exemplary semiconductor chip 100. As illustrated, the semiconductor chip 100 comprises one or more semiconductor devices 102a-102n (hereinafter collectively referred to as “semiconductor devices 102”), such as transistors, resistors, capacitors, diodes and the like deposited upon a substrate 104 and coupled via a plurality of wires or interconnects 106a-106n (hereinafter collectively referred to as “interconnects 106”). These semiconductor devices 102 and interconnects 106 share power, thereby distributing a thermal gradient over the chip 100 that may range from 100 to 180 degrees Celsius in various regions of the chip 100.
Many methods currently exist for performing thermal analysis of semiconductor chips designs, e.g., to ensure that a chip constructed in accordance with a given design will not overheat and trigger a failure when deployed within an intended system. Such conventional methods, however, typically fail to provide a complete or an entirely accurate picture of the chip's operating thermal gradient. For example, typical thermal analysis models attempt to solve the temperature on the chip substrate, but do not solve the temperature in a full three dimensions, e.g., using industry standards design, package and heat sink data. Moreover, most typical methods do not account for the sharing of power among semiconductor devices and interconnects, which distributes the heat field within the chip, as discussed above. As a result, thermal management systems designed manage internal temperatures and/or thermal gradients in the chip (and/or system incorporating the chip) in operation (e.g., by dissipating heat from the chip or warming specific locations on the chip) are inefficiently designed. In fact, typical thermal management systems are designed with little or no knowledge of actual chip temperatures and gradients at all. This often leads to chip and/or system failure due to overheating or waste as excess cooling resources are directed to regions in which they are not needed.
Therefore, there is a need in the art for a method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs.